1. Field of the Invention
The present invention relates to a solid-state imaging device used in a digital camera, a digital camcorder, an endoscope, and the like. Priority is claimed on Japanese Patent Application No. 2010-004996, filed Jan. 13, 2010, the content of which is incorporated herein by reference.
2. Description of the Related Art
In recent years, in the technical fields of digital cameras, digital camcorders, and endoscopes, an effort to reduce the size and power consumption of products has been made. In accordance with this, reductions in the size and power consumption of a solid-state imaging device have also been demanded. As an example of a solid-state imaging device, JP-A-2006-287879 proposes a solid-state imaging device in which an A/D converter is formed by a digital circuit in order to realize reductions in size and power consumption of the solid-state imaging device. In addition, in order to read a signal from a sensor at high speed, a column A/D type solid-state imaging device which has an A/D converter for every pixel column has been proposed (known technique).
FIG. 11 shows the configuration of an A/D converter 201 disclosed in JP-A-2006-287879. The A/D converter 201 includes a Ring Delay Line (RDL) 102, a counter circuit 103, and an RDL latch circuit 104.
The RDL 102 has a plurality of inverting circuits 101a which outputs input signals after inverting them and in which a delay time changes with a power supply voltage, and one NAND circuit 101b which operates in response to a pulse signal input to its one input terminal. The plurality of inverting circuits 101a and the one NAND circuit 101b are disposed in a ring shape, and an input voltage is applied to power supply terminals of the inverting circuit 101a and the NAND circuit 101b. As a result, the RDL 102 outputs a clock signal φORDL101 which has a frequency corresponding to the size of an input voltage.
The counter circuit 103 counts the number of times of falling of the clock signal φORDL101 output from the RDL 102, and outputs a count value φOCNT106 which indicates the number of times of circulation of the clock signal φORDL101 as binary digital data. The RDL latch circuit 104 holds the outputs from each inverting circuit 101a and the NAND circuit 101b, and outputs positional information φOLAT107 which indicates the position of the clock signal φOCNT101 in the RDL 102 as binary digital data from the held value.
In addition, a control signal output circuit 105 which outputs signals (a start pulse φRDLST102, a latch signal φRDLLAT103, a count enable signal φCNTEN104, a counter reset signal φCNTRST105) for controlling the blocks (the RDL 102, the counter circuit 103, and the RDL latch circuit 104) of the A/D converter 201 is provided separately.
Next, an operation of the A/D converter 201 disclosed in JP-A-2006-287879 will be described using a timing chart shown in FIG. 12. First, at a timing T101, the counter reset signal φCNTRST105 changes to “HIGH”. As a result, the count value φOCNT106 that the counter circuit 103 holds is reset. Then, at a timing T102, the counter reset signal φCNTRST105 changes to “LOW”. As a result, the counter circuit 103 ends the reset operation.
Then, at a timing T103, the start pulse φRLDST102 changes to “HIGH”. At the same time, the count enable signal φCNTEN104 changes to “HIGH”. As a result, the RDL 102 outputs the clock signal φORDL101 which has a frequency corresponding to the size of an input voltage. At the same time, the counter circuit 103 starts an operation of counting the falling of the clock signal φORDL101.
Then, at a timing T104, the latch signal φRDLLAT103 changes to “HIGH”. Then, at a timing T105, the count enable signal φCNTEN104 changes to “LOW”. At the same time, the latch signal φRDLLAT103 changes to “LOW”. As a result, the count operation of the counter circuit 103 ends. At the same time, the RDL latch circuit 104 holds the outputs of each inverting circuit 101a and the NAND circuit 101b. Then, at a timing T106, the start pulse φRDLST102 changes to “LOW”. As a result, the RDL 102 ends the output of the clock signal φORDL101.
By the operation described above, it is possible to obtain the count value φOCNT106 when a certain fixed period (T103 to T105) has elapsed and the positional information φOLAT107 of the clock signal φORDL101 in the RDL 102. Then, the A/D converter 201 outputs a digital signal, which has the count value φOCNT106 as a high-order bit and the positional information φOLAT107 as a low-order bit, as an A/D conversion result. By the above operation, the A/D converter 201 can obtain a digital signal corresponding to the size of the input voltage.
FIG. 13 shows the configuration of an A/D type solid-state imaging device in which the A/D converter 201 disclosed in JP-A-2006-287879 is provided for every pixel column in order to realize reductions in size and power consumption and to read a signal from a sensor at high speed. The solid-state imaging device shown in FIG. 13 includes a pixel array 2, a vertical scanning circuit 3, four A/D converters 201 (an ADC 1, an ADC 2, an ADC 3, and an ADC 4), an ADC latch circuit 5, a control signal output circuit 6, and a horizontal scanning circuit 7.
In the pixel array 2, pixels 1 each of which has at least a photoelectric conversion element and outputs a pixel signal φPIX1 corresponding to the amount of incident light are arrayed in a two-dimensional manner (4 rows×4 columns in the example shown in FIG. 13). The vertical scanning circuit 3 performs row selection of the pixel array 2 using pixel selection signals φV1 to φV4. The A/D converter 201 is disposed for every pixel column of the pixel array 2 and performs analog-to-digital conversion of a pixel signal φPIX1 read from the pixels 1. The ADC latch circuit 5 holds the output signal of the A/D converter 201. The control signal output circuit 6 outputs signals for controlling the A/D converter 201 and the ADC latch circuit 5. The horizontal scanning circuit 7 controls the ADC latch circuit 5 using column selection signals φH1 to φH4 so that the digital signals held in the ADC latch circuit 5 are output to the respective columns.
When the A/D converter 201 is provided for every pixel column, the horizontal width in which the A/D converter 201 can be disposed is restricted by the pixel pitch P (refer to FIG. 13). Accordingly, when the A/D converter 201 is provided for every pixel column, it is necessary to make the A/D converter 201 smaller than that in the related art. However, an invention for making the A/D converter 201 smaller has not yet been proposed.